Wafer-to-Wafer Process for Manufacturing a Stacked Structure

ABSTRACT

A method for fabricating a multi-chip stacked structure includes joining multiple wafers with interconnect structures interposed between each set of adjacent wafers. As each wafer is added to the stack, the new wafer is thinned to expose a through silicon via and back side metallization is performed. After the last wafer has been so joined, the wafer stack is diced and then joined to a substrate with a final interconnect structure interposed between the final wafer and the substrate.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application is a Continuation of co-pending U.S. patent application Ser. No. 13/671,098, filed on Nov. 7, 2012, the entire content of which is incorporated herein by reference.

BACKGROUND

1. Technical Field

The present disclosure generally relates to manufacturing a stacked structure, and more particularly, to wafer-to-wafer process for manufacturing a stacked structure.

2. Discussion of Related Art

In the field of wafer packaging, a three-dimensional (3D) packaging having a through-silicon via (TSV) may be created. The process of manufacturing the 3D packaging involves a glass handler to support thin silicon wafers during processing steps and to bond the thinned silicon chips onto another chip or substrate. The fragility of the wafers and the potential for warpage of the wafers makes positioning and bonding a challenging task. In addition the high thermal resistance of the glass makes high power testing effectively impossible.

BRIEF SUMMARY

A method for fabricating a multi-chip stacked structure includes joining multiple wafers with interconnect structures interposed between each set of adjacent wafers. As each wafer is added to the stack, the new wafer is thinned to expose a through silicon via and back side metallization is performed. After the last wafer has been so joined, the wafer stack is diced and then joined to a substrate with a final interconnect structure interposed between the final wafer and the substrate.

A method for fabricating a multi-chip stacked structure includes joining a first wafer and a second wafer with a first interconnect structure interposed therebetween to form a wafer stack. A gap between the first wafer and the second wafer is filled. The second wafer is thinned to expose a first through silicon via. A back side metallization process is performed on a surface of the second wafer having the exposed first through silicon via. The surface of the second wafer having the exposed first through silicon via of the wafer stack is joined to a third wafer with a second interconnect structure interposed therebetween, the third wafer having a second through silicon via. The third wafer is thinned to expose the second through silicon via. A back side metallization process is performed on a surface of the third wafer having the exposed second through silicon via. The wafer stack including the third wafer is diced. The wafer stack is joined to a substrate with a third interconnect structure interposed therebetween.

The third wafer may be a full thickness wafer. The joining of the first wafer and the second wafer to form the wafer stack may include a reflow process. The joining of the first wafer and the second wafer to form the wafer stack may include a thermal compression process or a vacuum bonding process.

The first wafer may be thinned prior to joining the wafer stack to the third wafer. An underfill material may be deposited between the wafer stack including the third wafer and the substrate. The underfill may be pre-applied on one of the wafers of the wafer stack prior to wafer bonding. An underfill material may be deposited on the wafer stack prior to joining the wafer stack to the substrate.

The first interconnect may be tested prior to joining the wafer stack to the third wafer and the second interconnect may be tested prior to joining the wafer stack to the substrate.

A method for fabricating a multi-chip stacked structure includes joining a first wafer and a second wafer with a first interconnect structure interposed therebetween to form a wafer stack. A gap between the first wafer and the second wafer is filled with underfill material. The underfill material is fully cured prior to the subsequent process steps. The second wafer is thinned to expose a first through silicon via. A back side metallization process is performed on a surface of the second wafer having the exposed first through silicon via. The wafer stack is joined to an additional wafer with an additional interconnect structure interposed therebetween, the additional wafer having an additional through silicon via. A gap between the additional layer and the wafer stack is filled. The additional wafer is thinned to expose the additional through silicon via. A back side metallization process is performed on a surface of the additional wafer having the exposed additional through silicon via. The steps of joining the wafer stack to an additional wafer having an additional through silicon via, filling the gap, thinning the additional wafer, and performing back side metallization are repeated until a desired number of additional wafers have been joined to the wafer stack. The surface of a final additional wafer is joined to a final wafer with a final interconnect structure interposed therebetween, the final wafer having a final through silicon via. The final wafer is thinned to expose the final through silicon via. A back side metallization process is performed on a surface of the final wafer having the exposed final through silicon via. The wafer stack including the final wafer is diced. The wafer stack is joined to a substrate with a substrate interconnect structure interposed therebetween.

The final wafer may be a full thickness wafer. The joining of the first wafer and the second wafer and the joining of the additional wafer stacks to the second wafer and to each other may include a reflow process. The joining of the first wafer and the second wafer and the joining of the additional wafer stacks to the second wafer and to each other may include a thermal compression process or a vacuum bonding process. The first wafer may be thinned prior to joining the wafer stack to the third wafer. An underfill may be deposited between the wafer stack including the final wafer and the substrate. Each interconnect of the first interconnect, the second interconnect, and the additional interconnects may be tested during the performance of the method.

Tested repair wiring routes may be incorporated in to the third wafer prior to depositing joining metallurgy in joining the wafer stack to the substrate.

A method for fabricating a multi-chip stacked structure includes joining a first wafer and a second wafer with a first interconnect structure interposed therebetween to form a wafer stack. A gap between the first wafer and the second wafer is filled with an underfill. The second wafer is thinned to expose a first through silicon via. A back side metallization process is performed on the wafer stack. The wafer stack is joined to a third wafer with a second interconnect structure interposed therebetween. The third wafer is thinned to expose a second through silicon via. A back side metallization process is performed on the wafer stack. The wafer stack is diced. The diced wafer stack is joined to a substrate with a third interconnect structure interposed therebetween.

Prior to joining the third wafer to the wafer stack, at least one intermediate stack may be joined to the wafer stack. Each of the at least one intermediate stacks may have an intermediate interconnect interposed between the intermediate stack and the wafer stack. Thinning may be performed on the intermediate stack to expose a corresponding through silicon via. Back side metallization may be performed on the intermediate stack.

The third wafer may be a full thickness wafer. The joining of the first wafer and the second wafer to form the wafer stack may include a reflow process. The joining of the first wafer and the second wafer to form the wafer stack may include a thermal compression process or a vacuum bonding process. A gap between the second wafer and the third wafer may be filled with an underfill. The underfill may be pre-applied on the second or third wafer prior to wafer bonding. An optical coupling or a winding channel or pourisity for cooling may be formed within an interconnect or underfill layer. Joining or bonding of the wafers may be performed under vacuum or thermal compression. One or more spacer posts may be formed on one or more of the wafers for gap control.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Exemplary embodiments of the present disclosure will be described below in more detail, with reference to the accompanying drawings:

FIGS. 1-3 illustrate a method for manufacturing a stacked structure according to exemplary embodiments of the present disclosure;

FIG. 4 is a flow diagram illustrating a method for manufacturing a stacked structure according to exemplary embodiments of the present disclosure;

FIGS. 5-7 illustrate methods for manufacturing a stacked structure according to exemplary embodiments of the present disclosure;

FIG. 8 is a flow diagram illustrating a method for manufacturing a stacked structure according to exemplary embodiments of the present disclosure;

FIG. 9 illustrates a stacked structure according to exemplary embodiments of the present disclosure;

FIG. 10 shows an inter chip cooling structure in a stacked structure according to exemplary embodiments of the present disclosure;

FIG. 11 illustrates a method of wafer joining using a vacuum apparatus in accordance with exemplary embodiments of the present disclosure; and

FIG. 12 is a schematic diagram illustrating a technique for filling underfill material using a vacuum apparatus in accordance with exemplary embodiments of the present disclosure.

DETAILED DESCRIPTION

According to exemplary embodiments of the present disclosure, a wafer-to-wafer method for manufacturing a stacked structure (e.g., 3D packaging or multiple chip stacking packaging) may eliminate the need for a backing substrate, such as glass or Si, and handling of the thinned silicon wafer during processing. In a wafer-to-wafer processing method, components of the stacked structure may be bonded with the support of a wafer to substantially ensure mechanical integrity and ease the handling. For example, a full-thickness functional wafer may be joined to a functional wafer of the stack, where the full-thickness functional wafer acts as the handler thereby eliminating the need for the backing substrate.

In forming the wafer stack, underfill may be inserted between the functional wafers to provide added structural integrity. Alternatively, the underfill may be applied to one of the wafers prior to the joining and/or bonding of the two wafer surfaces.

Exemplary embodiments of the present invention may utilize a repair scheme in which the bonded wafers are tested at each stage of bonding within the wafer stack so that any needed repair wiring may be incorporated into the wafer stack prior to applying the next wafer layer.

Further, during a bonding process step of the wafer-to-wafer method, mechanical procedures, such as using a vacuum apparatus for holding the wafer flat and applying pressure to the wafer stack, may be used to reduce the wafer warp-age of a bonded wafer structure. Exemplary embodiments of the present invention may utilize an integration scheme where the wafer stack is tested and repair wiring included in the next bonded wafer is included.

A built up stacking structure may be mechanically stronger than a single wafer or interposer, and may reduce a risk due to coefficient of thermal expansion (CTE) mismatching between a silicon wafer and a substrate. According to an exemplary embodiment of the present disclosure, because a glass backing structure is not present, the stacked structure can be tested at every step. Furthermore, defects may be corrected with rewiring in a later manufactured layer of the stacked structure. Through the use of a silicon substrate, high power testing may be employed.

According to an exemplary embodiment of the present disclosure, interposers can take more than one type of wafer and may be used to build a multi-chip module (MCM) in a single step.

Referring now to FIGS. 1-4, a wafer level method for fabricating multi-chip stacked structure includes joining a first wafer 101 and a second wafer 104 to form a wafer stack 100 (see FIG. 4, block 401). The first wafer 101 and the second wafer 104 may be joined by a first interconnect structure (e.g., 102 a). A gap between the first wafer and the second wafer may be filed using an underfill or filler 105 (see block 402). The underfill or filler may be applied after wafer bonding, or it may be pre-applied on one of the wafers before bonding.

The joining or bonding of the wafers may be performed in a vacuum or the like to flatten the wafers. FIG. 11 illustrates a method for performing vacuum assisted bonding in accordance with exemplary embodiments of the present disclosure. The pre-aligned wafer stack comprising the first wafer 1102 (or stacked wafers), the second wafer (1101), and spacers 1103 for controlling the wafer to wafer gap, is placed on a vacuum chunk 1104 having a flat surface. Vacuum pressure is applied through the vacuum chuck 1104 and accordingly, the second wafer 1101 is pulled downwards and flattened. A deformable membrane 105 capable of withstanding bonding temperature is placed over the wafer stack. The deformable membrane 105 may cover those vacuum holes of the vacuum chuck 1104 that are not covered by the wafer. When vacuum pressure is turned on, the vacuum chuck 104 will pull down the wafer that is in contact with the chuck (the second wafer 1101) and the air pressure on top of the membrane 105 will press down the top wafer (the first wafer 1102). The set of spacers 1103 may be inserted at the peripheral of the wafer pair to maintain a proper gap between the wafers 1101 and 1102. To provide increased planarity and gap control, spacers may be distributed on one of the wafers, by either photolithographical methods or spray or spin coating. The bonding may be achieved through the first interconnect structure, which may include solder, soft metal, metal, etc. Assembly under vacuum may be heated to form the joining.

Joining or bonding of the wafers may be performed by thermal compression or flip chip bonder.

The gap between joined wafer pair may be filled by underfill material to enhance the mechanical strength of the wafer pair, so that the wafer pair can be treated as one wafer for subsequent processes, such as wafer thinning and backside metallization. The underfill can be performed by capillary underfill or vacuum underfill after wafer bonding, or underfill can be applied to one of the wafer prior the bonding and form wafer bonding and underfill simultaneously. If vacuum underfill method is used after wafer bonding, the peripheral of the wafer pair may be sealed with a thin band of adhesive or underfill material except for a small opening. The wafer pair can be first evacuated by vacuum, followed by dipping the opening into the underfill material, and venting vacuum with air or inert gas to use external pressure to push the underfill material into the gap. Elevated temperature may be used to accelerate the filling process. This arrangement may be illustrated in FIG. 12, which is a schematic diagram illustrating a technique for filling underfill material using a vacuum apparatus in accordance with exemplary embodiments of the present disclosure. The underfill material may be cured prior the subsequent process.

Referring to FIG. 2, the second wafer 104 may be thinned to expose a first through silicon via (e.g., 103 a) (see block 403). A back side metallization process may be performed on a surface of the second wafer having an exposed first through silicon via (TSV) (see block 404). Thereafter, the process of joining additional wafers (401), providing underfill (402), thinning the additional wafer (403), and performing back side metallization (404) may be repeated for as many additional wafers as is desired.

The wafer stack 100, that may be treated as a single wafer, may be joined to a third wafer 106 having a second through silicon via (TSV) (e.g., 103 b) to the surface of the second wafer 104 having an exposed first through silicon via (e.g., 103 a) by a second interconnect structure (e.g., 102 b).

As exemplary embodiments of the present invention are not limited to the bonding of only three wafers, the process including joining wafers, deposited a filler, wafer thinning, and a back side metallization, may be repeated to formed additional layers, where desired.

A third interconnect structure (e.g., 106) may be formed, if needed (see block 405).

Referring to FIG. 3, the wafer stack including the third wafer, after thinning and metallization of the last wafer, may be diced (e.g., 103 x) (see block 406).

The wafer stack may then be joined to a substrate 107 and underfill may be performed (see block 407)

The underfill material adds strength, preserves the flatness of the wafer stack 100 and seals in the gap. The underfill material may be an electrically-insulating adhesive such as an over-bump applied resin (OBAR) or pre applied underfill which may be applied on one of the wafers prior to the wafer joining. The underfill material may be thermally conductive as to facilitate the heat flow through the staked layers.

A patternable material that can withstand bonding condition may be applied on one of the wafers and may serve as spacer for the bonding.

The grind (back) side metallization process may include a bumping process to form the second interconnect structure. The bumping process may be performed on the wafer to be joined to the wafer stack.

The bonding can be front side to front side or front side to back side. Further, the bonding may be symmetric to compensate for stress. For example, a wafer with tensile stress on the bonding surface may be joined to a wafer with compression stress on the bonding surface to minimize the curvature difference between the joining surfaces. The curvature of the wafer can be adjusted by depositing thin film stacks on the back surface of the wafer. Alternatively, the bonding tool can preferentially cool one of the bonded surfaced faster than the other to balance the wafer bow.

Since the wafer bonding is performed on two full thickness wafers, the wafers may be strong enough to withstand the wafer handling and mechanical pressure during the bonding process.

For a structure having a large number of layers, sub-stacks may be formed, for example, including two to four layer stacks. One of the wafers may be a full-thickness wafer wile the remaining wafers may be thinned. These sub-stacks may be joined face-to-face, followed by wafer thinning and backside metallization, to form a final packaging.

Referring now to FIGS. 5-8, a wafer level method for fabricating multi-chip stacked structure includes joining a first wafer 501 and a second wafer 504 to form a wafer stack 500 (see block 801). The first wafer 501 and the second wafer 504 may include respective first through silicon via (TSV) (e.g., 503 a) and second through silicon via (TSV) (e.g., 503 b). The first wafer 501 and the second wafer 504 may be joined by a first interconnect structure (e.g., 502 a). A gap between the first wafer and the second wafer may be filed using an underfill or filler 505 (see block 802). The second wafer 504 may be thinned to expose the second through silicon via (TSV) (e.g., 503 b) (see block 803).

The joining or bonding of the wafers may be performed in a vacuum or thermal compression or the like to flatten the wafers. The bonding may be achieved through the first interconnect structure, which is a solder, soft metal, metal, etc. Spacer posts (not shown) may be formed on one of the wafers for gap control.

Referring to FIG. 6, a back side metallization process may be performed on a surface of the second wafer 504 having an exposed second through silicon via (TSV) (see block 804). Thereafter, the steps of joining additional wafers using an additional interconnect structure (810), performing underfill (802), thinning the additional wafer (803), and providing back side metallization may be repeated for as many additional wafers are desired.

A process including joining wafers, deposited a filler underfill, wafer thinning, and a back side metallization, may be repeated to formed additional layers. Additional layers may also be form by depositing the underfill on the solder side, including joining wafers, thinning the joined wafer, and a back side metallization. In so doing, the wafer stack 500 may be joined to a third wafer 506 having a third through silicon via (TSV) (e.g., 503 c) to the surface of the second wafer 504 having an exposed second through silicon via (TSV) (e.g., 503 b) by a second interconnect structure (e.g., 502 b).

From this point, two possible courses of action are possible (805). According to the first course of action, a fourth wafer may be joined and underfill provided (806). Thereafter the first wafer may be thinned and back side metallization performed (807).

According to the second course of action, the stack may be joined to a glass handler (808). Then, referring to FIG. 7, the first wafer 501 may be thinned to expose the first through via (e.g., 503 a) and a back side metallization process may be performed on an exposed surface of the first wafer 501 (see block 809). The first wafer 501 may be joined to a fourth wafer 506 (see block 810) by a third interconnect structure 502 x. The glass handler may then be released (811). An underfill material (not shown) may be disposed between the first wafer 501 and the fourth wafer 506 prior or after the bonding.

Then, regardless of the course of action taken, the wafer stack including the third wafer and the fourth wafer may be thinned to expose a lower through silicon via (TSV) (e.g., 503 x) and back side metallization and forming of fourth interconnect structure may optionally be performed on the exposed lower though silicon via (e.g., 503 x) (see block 812). The wafer stack may be diced. Dicing may be performed and the wafer stack may be joined to a substrate 508 by a fourth interconnect structure (e.g., 507) and underfill may be performed (see block 813).

The method of FIG. 8 may be modified, wherein a back side metallization process may be performed on the wafer stack of block 805. Here the stack may be laminated to a glass or thick wafer handler. The handler may be removed at a later time, e.g., prior to block 809, 810, or 811.

The thickness of the final wafer stack may be further reduced by thinning the outer wafer that theretofore had full thickness. The thinning of the outer wafer may be performed before it is diced and joined to substrate.

According to an exemplary embodiment of the present disclosure, a device formed according to FIGS. 1-8 may be tested during manufacturing (before and after bonding), wherein interconnect structures are successively exposed. Similarly, the ability to test during manufacturing enables the repair of defects in later formed layers by rewiring, for example, at block 405 of FIG. 4 or block 805 of FIG. 8.

Referring to FIG. 9, a device according to an exemplary embodiment of the present disclosure is shown. The thinner stack of this arrangement has a lower thermal resistance. The devices are diced after the wafer stack is formed and the gaps are filled at the wafer level. The chip may have a clean upper edge 901. An adhesive (underfill) layer 902 may be formed between the wafer stack and the substrate.

As described above, according to exemplary embodiments of the present disclosure, joining may be performed before thinning the die. In this method, a glass handler lamination and delamination process may be eliminated.

According to an exemplary embodiment of the present disclosure, a multiple chip carrier interposer can be thin and may be, for example, between approximately 10 microns to approximately 2000 microns, for example, between 20 microns and 700 microns.

Referring to FIG. 10, additional structures may be formed in the interconnect and underfill layers. FIG. 10 illustrate a winding channel than may be used for liquid cooling in accordance with exemplary embodiments of the present disclosure. These additional structures may include an optical coupling, inter chip cooling apparatus, or the like.

According to an exemplary embodiment of the present disclosure, a wafer and a Multi-Chip Module (MCM) interposer may be used to join multiple chips on same wafer to form a direct MCM packaging.

Although illustrative embodiments of the present disclosure have been described herein with reference to the accompanying drawings, it is to be understood that the disclosure is not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims. 

1-24. (canceled)
 25. A multi-chip stacked structure, comprising: a substrate; a top wafer having a first thickness; and at least one intermediate wafers disposed between the substrate and the top wafer, each of the at least one intermediate wafers having a second thickness that is less than the first thickness, wherein each of the at least one intermediate wafers includes at least one through silicon via, wherein each of the at least one intermediate wafers has a backside metallization disposed thereon; wherein an interconnect structure is interposed between the top wafer and the at least one intermediate wafers as well as between each of the at least one intermediate wafers; wherein a gap-filling material fills a gap between the top wafer and the at least one intermediate wafers as well as between each of the at least one intermediate wafers.
 26. The multi-chip stacked structure of claim 25, wherein the interconnect structure is also disposed between the substrate and the at least one intermediate wafers.
 27. The multi-chip stacked structure of claim 25, wherein the first thickness of the top wafer is a full wafer thickness and the second thickness of the at least one intermediate wafers is a thinned-wafer thickness.
 28. The multi-chip stacked structure of claim 25, wherein the at least one intermediate wafers are joined to each other by a reflow process.
 29. The multi-chip stacked structure of claim 25, wherein the at least one intermediate wafers are joined to the top wafer by a reflow process.
 30. The multi-chip stacked structure of claim 25, wherein the at least one intermediate wafers are joined to each other by a thermal compression process or a vacuum bonding process.
 31. The multi-chip stacked structure of claim 25, wherein the at least one intermediate wafers are joined to the top wafer by a thermal compression process or a vacuum bonding process.
 32. The multi-chip stacked structure of claim 25, wherein the gap-filling material additionally fills a gap between the at least one intermediate wafers and the substrate.
 33. The multi-chip stacked structure of claim 25, wherein each of the at least one intermediate wafers and the interconnect structure thereof is configured to be independently tested.
 34. The multi-chip stacked structure of claim 25, wherein the at least one intermediate wafers includes at least four intermediate wafers.
 35. The multi-chip stacked structure of claim 25, further including spacers disposed between the top wafer and the at least one intermediate wafers and between each of the at least one intermediate wafers, the spacers configured to maintain a desired separation between the top wafer and the at least one intermediate wafers and between each of the at least one intermediate wafers.
 36. A multi-chip stacked structure comprising: a vacuum chuck; a first wafer disposed on the vacuum chuck; a second wafer disposed on the first wafer, including at least one thorough silicon via, and having a backside metallization disposed thereon; an interconnect structure interposed between the first wafer and the second wafer; a gap-filling material disposed within a gap between the first and second wafers; and a deformable membrane disposed over the second wafer.
 37. The multi-chip stacked structure of claim 36, wherein the vacuum chuck includes a plurality of holes and the deformable membrane covers each of the plurality of holes of the vacuum chuck that are not covered by the first wafer.
 38. The multi-chip stacked structure of claim 36, wherein the deformable membrane is affixed to the first wafer and the vacuum chuck by vacuum pressure of the vacuum chuck.
 39. The multi-chip stacked structure of claim 36, wherein the first wafer is thicker than the second wafer.
 40. The multi-chip stacked structure of claim 39, wherein the first wafer is a full-thickness wafer and the second wafer is a thinned wafer.
 41. The multi-chip stacked structure of claim 36, wherein the first wafer and the second wafer are joined to each other by a vacuum bonding process.
 42. The multi-chip stacked structure of claim 36, wherein each of the first and second wafers is configured to be independently tested.
 43. The multi-chip stacked structure of claim 36, further including spacers disposed between the first and second wafers, the spacers configured to maintain a desired separation between the first and second wafers. 